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1/11 october 2002 n supply voltage range: 4v to 5.5v n typical peak output current: (source 2a, sink 3.5a) n operating frequency: 30 to 750 khz n smart turn-off anticipation timing n automatic turn off for duty cycle less than 14% n possibility to operate in discontinuous mode description stsr3 smart driver ic provides a high current outputs to properly drive secondary power mosfets using as synchronous rectifier in low output voltage, high efficency flyback converters. from a synchronouzing clock input, withdrawn on the secondary side of the isolation transformer, the ic generates a driving signal with set dead times with respect to the primary side pwm signal. the ic operation prevents secondary side shoot-through conditions at turn-on of the primary switch providing anticipation in turn-off the output. this smart function is implemented by a fast cycle-after-cycle logic control mechanism, based on a high frequency oscillator synchronized by the clock signal. this anticipation is externally set through external component. a special inhibit function allows to shut-off the drive output. this feature makes discontinuous conduction mode possible and avoids reverse conduction of the synchronous rectifies. stsr3 synchronous rectifiers smart driver for flyback peak detector bias uvlo ck vcc 6 5.7v 8 4 2 output buffer 1 n/c pwrgnd sglgnd anticipation set 3 5 inhibit 25mv - + digital control high frequency oscillator 7 + + + out gate setant schematic diagram so-8
stsr3 2/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. (*) a higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10ma maximum thermal data (*) this value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 c/w can be obtained improving thermal conductivity of the board ordering codes connection diagram (top view) symbol parameter value unit v cc dc input voltage -0.3 to 6 v v outgate max gate drive output voltage -0.3 to v cc v v inhibit max inhibit voltage (*) -0.6 to v cc v v ck clock input voltage range (*) -0.3 to v cc v p tot continuous power dissipation at t a =105c without heatsink 270 mw esd human body model pins 1,,2, 4, 5, 6, 7, 8 1kv pin 3 0.9 kv t stg storage temperature range -55 to +150 c t op operating junction temperature range -40 to +125 c symbol parameter so-8 unit r thj-amb thermal resistance junction-case 40 c/w r thj-amb thermal resistance junction-ambient (*) 160 c/w type so-8 so-8 (t&r) stsr3 stsr3cd STSR3CD-TR
stsr3 3/11 pin description pin n symbol name and function 1 nc no internally connected 2v cc the supply voltage range from 4.0v to 5.5v allows applications with logic gate threshold mosfets. uvlo feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage. 3 set ant the voltage on this pin sets the anticipation (t ant1 ) in turning off the out gate it is possible to choose among three different anticipation times by discrete partitioning of the supply voltage. 4 ck this input provides synchronization for ics operations, being the transitions between the two output conditions based on a positive threshold, equal for the two slopes. a smart internal control logic mechanism using a 15mhz internal oscillator generates proper anticipation timing at the turn-off of each output. this feature allows safe turn-off of synchronous rectifiers avoiding any eventual shoot-through situation on secondary side at both transitions. smart clock revelation mechanism makes these operations independent by false triggering pulses generated in light load conditions and by particular demagnetization techniques.absolute maximum voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10ma max. 5 inhibit this input enables out gate to work when its voltage is lower than the negative threshold voltage (v inhibit v h the out gate will be high for a minimum conduction time (t on(gate) ). in typical forward converter application, it is possible to turn off the freewheeling mosfet when the current through it tends to reverse, allowing discontinuous conduction mode and providing protection to the converter from eventual sinking current from the load.absolute maximum voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10ma max. 6 sglgnd reference for all the control logic signals. this pin is completely separated from the pwrgnd to prevent eventual disturbances to affect the control logic. 7out gate gate drive signal for freewheeling mosfet. anticipation [t ant ] in turning off out gate is provided during the transition in which the clock input goes to high when the clock input goes to high level. 8 pwrgnd reference for power signals, this pin carries the full peak currents for the two outputs.
stsr3 4/11 electrical characteristics (v cc =5v, ck= 250khz, duty-cycle=50%, v inhibit =-200mv, t j =-40 to 125c, unless otherwise specified.) note1: t r is measured between 10% and 90% of the final voltage; t f is measurerd between 90% and 10% on the initiual voltage note2: parameter guaranteed by design symbol parameter test conditions min. typ. max. unit supply input and under voltage lock out v ccon start threshold 3.8 4 v v ccoff turn off threshold after start 3.5 3.6 v v z zener voltage ck=0v i z = 2ma 5.5 5.8 6 v i cc unloaded supply current out gate = no load 15 20 ma ck=0v out gate = no load 3 5 gate driver outputs v ol output low voltage i outgate =-200ma 0.10 0.16 v v oh output high voltage i outgate =200ma 4.70 4.85 v i out output source peak current 2a output sink peak current 3.5 r out output series source resistance i outgate =-200ma 0.75 1.5 w output series sink resistance i outgate =200ma 0.5 0.8 t r out gate1,2 rise time c load =5nf (note 1) 40 ns t f out gate1,2 fall time c load =5nf (note 1) 30 ns t p clock propagation delay to turn on of out gate no load 50 ns turn-off anticipation time t ant out gate turn-off anticipation time v ant = 0 to 1/3v cc ; no load 75 ns v ant = 1/3v cc to 2/3v cc ; no load 150 v ant = 2/3v cc to v cc ; no load 225 i setant leakage current (note 2) -0.1 0.1 m a inhibit out gate2 enable v h threshold voltage t j = 25c -30 -25 mv i h leakage current (note 2) v inhibit = 200mv -400 na v inhibit = -200mv 1 m a t on(gate) minimum out gate on time v inhibit = +200mv 250 ns synchronization input v ck reference voltage t j = 25c 2.6 2.8 v d off duty cycle shut down t j = 25c 13 14 % duty cycle turn on after shut down t j = 25c 18 20
stsr3 5/11 timing diagram application information : stsr2 in forward converter secondary side notes 1) ceramic capacitors c1 and c2 must be placed very close to the ic; 2)r1andr2settheanticipationtimebypartitioningthevccvoltage; 3) r3 and r4 is a resistor divider meant to provide the correct ck voltage range; 4) r5 limits the current flowing through diode d2 when freewheeling drain voltage is high; 5) d1 could be necessary to protect inhibit pin from negative voltages. 6) d2 could be necessary to protect inhibit pin from voltages higher than vcc 7) d3 could be necessary to protect ck pin from voltages higher than vcc. 8) sglgnd layout trace must not include out gate current paths. 9) a capacitor in parallel with r4 could be necessary to eliminate turn off voltage spike. +5v +5v vout vin +5v cout c2 100nf r1 r2 r3 r4 d1 d2 c1 100nf r5 stsr3 4 5 7 8 2 6 3 ck inhibit outgate pwrgnd vcc sglgnd setant transformer mosfetn d3 pwm feedback loop option
stsr3 6/11 example of components selection for a forward converter forward specification: v in =36-72v v out =3.3v n=np/ns=4.5 r 3 and r 4 are calculated assuring a minimum voltage of 2.8v at ck pin. at 36v input, the voltage on the secondary winding is 36/4.5=8v. choosing r 3 =1.5k w ,r 4 results to be: r 4 =1k w is chosen. at 72v input the current at ck pin is calculated as: this value is below the maximum allowable current flowing into the ck pin (10ma). if the 10ma value is exceeded an external diode connected to v cc must be added (d3). r 1 and r 2 values set the anticipation time for out gate .forr 1 = and r 2 =0, t ant =75ns; for r 1 =r 2 =10k w ,t ant =150ns; for r 1 =0 and r 2 = ,t ant =225ns. the rc group composed by r 5 and the parasitic capacitance of inhibit pin (typically 5pf) delays the signal on inhibit comparator. this delay must be lower than 200ns. this condition imposes a maximum value for r 5 of about 20k w . in general a suggested value for r 5 is 10k w . at 72v input, the secondary voltage is 16v, so the maximum current flowing into inhibit pin is 16v/10k w =1.6ma which is below the maximum allowable current for the pin (10ma). if the 10ma value is exceeded an external diode (d2) connected to v cc must be added. the maximum negative voltage of C0.6v must be guaranteed for the inhibit pin. if this negative voltage is exceeded the current must be limited to 50ma. if necessary, a diode (d1) connected to sglgnd can be added to satisfy this specification. r 4 v ck i ck 2.8 () r 3 + v in i ck 2.8 () C r 3 v ck C --------------------------------------------------------------- - 3 1k w 2.8v 220 m a1.5k w + 8v 220 m a C 1.5k w 2.8v C ------------------------------------------------------------------------- - 965 w == i ck v in max () v cc C 0.3 C r 3 ----------------------------------------------------- 16 5 C 0.3 C 1.5k w ----------------------------- - 7.13ma ===
stsr3 7/11 inhibit operation of out gate in discontinuous conduction mode inhibit operation of out gate
stsr3 8/11 typical performance characteristics (unless otherwise specified t j =25c figure 1 : zener characteristics figure 2 : rise and fall time vs load capacitor figure 3 : out gate vs characteristics figure 4 : sink-source on resistance vs temperature figure 5 : clock threshold voltage vs temperature figure 6 : inhibit threshold voltage vs temperature
stsr3 9/11 figure 7 : supply current vs load capacitor figure 8 : supply current vs clock frequency figure 9 : gate on time vs temperature figure 10 : duty cycle shut down vs temperature figure 11 : duty cycle turn on after shut down vs temperature figure 12 : clock leakage current vs clock voltage
stsr3 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45? (typ.) d 4.8 5.0 0.189 0.196 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.149 0.157 l 0.4 1.27 0.015 0.050 m 0.6 0.023 s ? (max.) so-8 mechanical data 0016023 8
stsr3 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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